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toshiba confidential TC58NVG5T2HTA00 2011-03-23c 1 tentative toshiba mos digital inte grated circuit silicon gate cmos 32 gbit (4g ? 8 bit) cmos nand e 2 prom (triple-level-cell) description the TC58NVG5T2HTA00 is a single 3.3 v 32 gbit (40, 478,441,472 bits) nand electrically erasable and programmable read-only memory (nand e 2 prom) organized as (8192 ? 1024) bytes ? 516 pages ? 1064 blocks. the device has one 9216-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 9216-byte increments. the erase operation is implemented in a single block unit (4128 kbytes ? 516 kbytes:9216 bytes ? 516 pages). the TC58NVG5T2HTA00 is a serial-type memory device wh ich utilizes the i/o pins for both address and data input/output as well as for command in puts. the erase and program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recordin g, image file memory for still cameras and other systems which require high-d ensity non-volatile memory data storage. features ? organization TC58NVG5T2HTA00 device capacity 9216 ? 516 ? 1064 ? 8 bits register 9216 ? 8 page size 9216 bytes block size (4128k ? 516k) bytes ? modes read, reset, auto page program, auto block erase, status read, multi page program, multi page read ? mode control serial input/output command control ? number of valid blocks min 1028 blocks max 1064 blocks ? power supply v cc ? 2.7 v to 3.6 v ? access time cell array to register 150 ? s max (tbd) serial read cycle 25 ns min ? program/erase time auto page program tbd ? s/page typ. auto block erase 3 ms/block typ. ? operating current read (25 ns cycle) 50 ma max. program (avg.) 50 ma max. erase (avg.) 50 ma max. standby 100 ? a max.(tbd) ? package tsop i 48-p-1220-0.50c (weight: 0.53 g typ.) ? for reliability guidance, please refer to the application notes and comments (14). 60 bit ecc each 1k bytes required. free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 2 pin assignment (top view) pin names i/o1 ~ i/o8 i/o port ce chip enable we write enable re read enable cle command latch enable ale address latch enable wp write protect by / ry ready/busy v cc power supply v ss ground n.c no connection vss nc nc nc i/o8 i/o7 i/o6 i/o5 nc nc vcc v cc v ss nc vcc nc i/o4 i/o3 i/o2 i/o1 nc nc nc vss 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 vcc vss nc nc nc nc by / ry re ce nc nc v cc v ss nc nc cle ale we wp nc nc nc vss vcc ? 8 ? 8 TC58NVG5T2HTA00 free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 3 block diagram absolute maximum ratings symbol rating value unit v cc power supply voltage ? 0.6 to 4.6 v v in input voltage ? 0.6 to 4.6 v v i/o input /output voltage ? 0.6 v to v cc ? 0.3 v ( ? 4.6 v) v p d power dissipation 0.3 w t solder soldering temperature (10 s) 260 c t stg storage temperature ? 55 to 150 c t opr operating temperature 0 to 70 c capacitance * (ta ? 25c, f ? 1 mhz) symb0l parameter condition min max unit c in input v in ? 0 v ? 10 pf c out output v out ? 0 v ?? 10 pf * this parameter is periodically sampl ed and is not tested for every device. i/o control circuit status register command register column buffer column decoder data register sense amp memory cell array control circuit hv generator row address decoder logic control by / ry i/o1 v ss i/o8 ce cle ale we re by / ry row address buffer decoder to wp address register v cc free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 4 valid blocks * symbol parameter min typ. max unit n vb number of valid blocks 1028 ? 1064 blocks note: the device occasionally contains unus able blocks. refer to application note (10) toward the end of this document. the first block (block 0) is guaranteed to be a valid block at the time of shipment. the specification for the minimum number of valid blocks is applicable over the device lifetime. recommended dc operating conditions symbol parameter min typ. max unit v cc power supply voltage 2.7 v ? 3.6 v v v ih high level input voltage 2.7 v ? v cc ? 3.6 v 0.8 x vcc ? v cc ? 0.3 v v il low level input voltage 2.7 v ? v cc ? 3.6 v ? 0.3 * ? 0.2 x vcc v * ? 2 v (pulse width lower than 20 ns) dc characteristics (ta ? 0 to 70c, v cc ? 2.7 v to 3.6 v) symbol parameter condition min typ. max unit i il input leakage current v in ? 0 v to v cc ? ? ? 10 ? a i lo output leakage current v out ? 0 v to v cc ? ?? ? 10 ? a i cco0 power on reset current ? ?? ? 30 ma ? i cco1 serial read current ce ? v il , i out ? 0 ma, tcycle ? 50 ns ? ? 50 ma i cco2 programming current ? ?? ? 50 ma i cco3 erasing current ? ? ? 50 ma i ccs standby current ce ? v cc ? 0.2 v, wp ? 0 v/v cc ? ? 100 ? a v oh high level output voltage i oh ? ? 0.4 ma (2.7 v ? v cc ? 3.6 v) 2.4 ? ? v v ol low level output voltage i ol ? 2.1 ma (2.7 v ? v cc ? 3.6 v) ? ? 0.4 v i ol ( by / ry ) output current of by / ry pin v ol ? 0.4 v (2.7 v ? v cc ? 3.6 v) ? 8 ? ma free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 5 ac characteristics and recommended operating conditions (ta ? 0 to 70c, v cc ? 2.7 v to 3.6 v) symbol parameter min max unit t cls cle setup time 12 ? ns t cls2 cle setup time 42 ?? ns t clh cle hold time 10 ? ns t cs ce setup time 20 ? ns t cs2 ce setup time 32 ?? ns t ch ce hold time 10 ? ns t wp write pulse width 12 ? ns t als ale setup time 12 ? ns t alh ale hold time 10 ? ns t ds data setup time 10 ? ns t dh data hold time 5 ? ns t wc write cycle time 25 ? ns t wh we high hold time 10 ? ns t adl * we high hold time from final address to first data 300 ?? ns t ww wp high to we low 100 ? ns t rw ready to we falling edge 20 ?? ns t rp read pulse width 12 ?? ns t rc read cycle time 25 ? ns t rea re access time ? 20 ns t cr ce low to re low 10 ? ns t clr cle low to re low 10 ? ns t ar ale low to re low 10 ? ns t rhoh data output hold time from re high 25 ? ns t rloh data output hold time from re low 5 ?? ns t rhz re high to output high impedance ?? 60 ns t chz ce high to output high impedance ? 30 ns t clhz cle high to output high impedance ? 30 ? ns t reh re high hold time 10 ? ns t ir output-high-impedance-to- re falling edge 0 ? ns t rhw re high to we low 30 ? ns t whc we high to ce low 30 ? ns t whr we high to re low for data output 300 ? ns t whrs we high to re low for status & id read 180 ? ns t r memory cell array to starting address ? 150(tbd) ? s t wb we high to busy ? 100 ns t rst device reset time (ready/read/program/erase) ? 10/20/30/200 ? s * tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 6 ac test conditions condition parameter 2.7 v ? v cc ? 3.6 v input level 0 v to vcc input pulse rise and fall time 3ns input comparison level vcc/2 output data comparison level vcc/2 output load c l (50 pf) ? 1 ttl note: busy to ready time depends on the pull-up resistor tied to the by / ry pin. (refer to application note (6) toward the end of this document.) programming and erasing characteristics (ta ? 0 to 70c, v cc ? 2.7 v to 3.6 v) symbol parameter min typ. max unit notes t prog average programming time ? tbd tbd ? s t dcbsyw1 data cache busy time in write cache (following 11h) ?? ?? 10 ?? s t dcbsyw2 data cache busy time in write cache (following 15h) ?? tbd ? tbd ?? s (2) t dcbsyw3 data cache busy time in write cache (following 1ah) ?? 10 ? tbd ?? s (3) n number of partial program cycles in the same page ? ? ? (1) t berase block erasing time ? 3 10 ms (1) refer to application note (9) toward the end of this document. (2) t dcbsyw2 depends on the timing between internal programming time and data in time. (3) in case of program operation with data cache, t dcbsyw3 depends on the timing between internal programming time and data in time. data output when treh is long, output buffers are disabled by / re=high, and the hold time of data output depend on trhoh (25 ns min). on this condition, wa veforms look like normal serial read mode. when treh is short, output buffers are not disabled by /re=high, and the hold time of data output depend on trloh (5ns min). on this condition, output buffers are disabled by the rising edge of cle, ale, /ce or falling edge of /we, and waveforms look like extended data output mode. data output can be output synchronously with the clock after 05h+address*5cycle+e0h sequence. free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 27 id read operation timing diagram : v ih or v il we cle re t cr ce ale i/o t ar id read command address 00 maker code t rea t cls t cs t ds t ch t alh t als t cls t cs t ch t alh t dh 90h 00h 98h t rea t rea t rea see table 5 t rea see table 5 see table 5 t rea see ta b l e 5 see table 5 free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 28 pin functions the device is a serial access memory which utiliz es time-sharing input of address information. command latch enable: cle the cle input signal is used to control loading of the operation mode command into the internal command register. the command is latched into the command regi ster from the i/o port on the rising edge of the we signal while cle is high. address latch enable: ale the ale signal is used to control loading address in formation into the internal address register. address information is latched into the address register from the i/o port on the rising edge of we while ale is high. chip enable: the device goes into a low-power standby mode when ce goes high during the device is in ready state. the ce signal is ignored when device is in busy state ( by / ry ? l), such as during a program or erase or read operation, and will not enter standby mode even if the ce input goes high. write enable: the we signal is used to control the acqu isition of data from the i/o port. read enable: the re signal controls serial data output. data is available t rea after the falling edge of re . the internal column address counter is also increme nted (address = address + l) on this falling edge. i/o port: i/o1 to 8 the i/o1 to 8 pins are used as a port for transferring address, command and input/ output data to and from the device. write protect: the wp signal is used to protect the de vice from accidental programming or erasing. the internal voltage regulator is reset when wp is low. this signal is usua lly used for protecting the data during the power-on/off sequence when input signals are invalid. ready/busy: the by / ry output signal is used to indicate th e operating condition of the device. the by / ry signal is in busy state ( by / ry = l) during the program, erase and read operations and will return to ready state ( by / ry = h) after completion of the operation. the output buff er for this signal is an open drain and has to be pulled-up to vcc with an appropriate resister. ce we re wp by / ry free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 29 schematic cell layout and address assignment the program operation works on page units wh ile the erase operation works on block units. a page consists of 9216 bytes in which 8192 bytes are used for main memory storage and 1024 bytes are for redundancy or for other uses. 1 page ? 9216 bytes 1 block ? 9216 bytes ? 516 pages ? (4128k ? 516k)bytes capacity ? 9216 bytes ? 516 pages ? 1064 blocks an address is read in via the i/o port over five consecutive clock cycles , as shown in table 1. table 1. addressing i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 first cycle ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second cycle l l ca13 ca12 ca11 ca10 ca9 ca8 third cycle l pa6 pa5 pa4 pa3 pa2 pa1 pa0 ca0 to ca13: column address pa0 to pa18: page address pa0 to pa6: wl address in a block pa7: left / right plane address (left plane=0 / right plane=1) pa8 to pa18: block address fourth cycle pa14 pa13 pa12 pa11 pa10 pa9 pa8 pa7 fifth cycle l l l l pa18 pa17 pa16 pa15 note) (a) block address (pa8 to pa18) can only be selected between block 0 and block 1063. (b) wl address in a block (pa0 to pa6) can only be selected between wl 0 and wl 85. (c) there are lower/middle/upper address in a wl, which is selected 01/02/03h command. input of the address other than specified above is invalid. if those unspecified addresses are inpu tted in program or erase operation, th e device will output a fail status to respond to status read command. in case of read operation, some invalid data will be outputted by the device. please refer to application note (11) toward the end of this document for block management. 9216 549024 pages 1064 blocks 8192 8192 1024 1024 page buffe r data cache i/o8 i/o1 516 pages ? 1 block 8i/o free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 30 left / right plane scheme of nand 1 district of this nand consists of left / right plane 8kbyte page. left / right plane scheme is as follows. block arrangement the device has block gaps and chip gap( s). block arrangement is as follows. block x, left plane block x, right plane 8kbyte page 8kbyte page 1 district(32gbit) : 2 x 8kbyte page data cache 1064 blocks blockx consists of left plane and right plane block 0[left plane] 1064 blocks block gap block gap block gap block gap chip gap 00000h page address (hexadecimal) 00100h 00056h 00156h 00200h 00256h 84f00h 84f56h block 0[right plane] block 1[left plane] block 1[right plane] block gap 00300h 00356h block 1063[right plane] free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 51 id read the device contains id codes which can be used to iden tify the device type, the ma nufacturer, and features of the device. the id codes can be read out under the following timing conditions: table 5. code table description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 hex data 1st data maker code 1 0 0 1 1 0 0 0 98h 2nd data device code 1 1 0 1 0 1 1 1 d7h 3rd data chip number, cell type ? ? ? ? ? ? ? ? see table 4th data page size, block size, redundant size, organization ? ? ? ? ? ? ? ? see table 5th data extended block ? ? ? ? ? ? ? ? see table 6th data technology code ? ? ? ? ? ? ? ? see table 2nd data description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 hex data 8 gbits 1 1 0 1 0 0 1 1 d3h 16 gbits 1 1 0 1 0 1 0 1 d5h 32 gbits 1 1 0 1 0 1 1 1 d7h 64 gbits 1 1 0 1 1 1 1 0 deh 128 gbits 0 0 1 1 1 0 1 0 3ah memory density per each /ce 256 gbits 0 0 1 1 1 1 0 0 3ch 3rd data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 internal chip number per each ce/ 1 2 4 8 0 0 1 1 0 1 0 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 1 1 0 1 0 1 reserved 0 or 1 0 0 or 1 0 or 1 id read command address 00 1 st data 2 nd data 4 th data 90h 00h 98h see table 5 see table 5 see table 5 we cle re t cr ce ale i/o t ar t rea see table 5 3 rd data 5 th data see table 5 6 th data free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 52 4th data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 page size (without redundant area) 2 kb 4 kb 8 kb reserved 0 0 1 1 0 1 0 1 default value 1 0 0 block size (without redundant area) reserved 0 or 1 0 or 1 default value 0 0 0 redundant area size reserved 0 or 1 0 or 1 5th data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 district number per each /ce 1 2 4 8 0 0 1 1 0 1 0 1 reserved 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 6th data description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 130 nm process 0 0 0 90 nm process 0 0 1 70 nm process 0 1 0 56 nm process 0 1 1 43 nm process 1 0 0 32 nm process 1 0 1 24 nm process 1 1 0 technology code reserved 0 or 1 1 1 1 reserved 0 or 1 0 or 1 0 or 1 0 or 1 free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 56 application notes and comments (1) power-on/off sequence: the device is designed to offer protection from an y involuntary program/erase during power-transitions. an internal voltage detector di sables all functions whenever v cc is below about 2v. the reset command(ffh) must be issued to all s ce as the first command after the nand flash device is powered on. each ce will be busy for a maximum of 5ms after a reset command is issued. in this time period, the acceptable command is 70h/71h/f1h. each nand die will draw no more than 1st prior to execution of th e first reset command(ffh) after the device is powered on. wp pin provices hardware protection an d is recommended to be kept at v il during power-up and power-down. the two step command sequence for progra m/erase provides addition al software protection. 100us tcls twp twb 5ms max operation tds tdh tcs tclh 1ms min 2.5v 2.5v 2.5v 0.5v 0.5v ff h vcc ce cle ale wp we re i/on r/b 2.7v 2.7v 2.7v free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 57 (2) prohibition of unspecified commands the operation commands are listed in t able 3. input of a command other th an those specified in table 3 is prohibited. stored data may be co rrupted if an unknown command is entered during the command cycle. (3) restriction of commands while in the busy state during the busy state, do not input any command except 70h(71h) and ffh. free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 62 (10) invalid blocks (bad blocks) the device occasionally contains unusable blocks. therefore, the following issues must be recognized: at the time of shipment, the bad bl ock information is marked on each bad block. please do not perform an erase operation to bad blocks. it may be impossible to recover the bad block information, if the information is erased. check if the device has any bad blocks after installation into the system. refer to the test flow for bad block detection. bad blocks which are detected by the test flow must be managed as unusable blocks by the system. a bad block does not affect the perfor mance of good blocks because it is isolated from the bit lines by select gates. the number of valid blocks over th e device lifetime is as follows: min typ. max unit valid (good) block number 1028 ?? 1064 block bad block test flow regarding invalid blocks, bad block mark is in both the 1st and the last page. * 1:no erase operation is allowed to detected bad blocks * 2: bad column detection shoud be operated before detecting bad block information and bad columns should be skipped when bad block information is read. (for example) in case of column 0 or 8192 is bad column, column 2(4,6,8,10, ) or 8194(8196,8198,8200,8202, ) should be checked after column 0 or 8192. *3: at first, all blocks should be erased. bad block bad block pass read ffh check column 0 or 8192 of the first page start if fail block no ? 1 block no. ? block no. ? 1 last block end yes no read ffh check column 0 or 8192 of the last page entry bad block *1 if fail pass all block erase*3 free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 63 (11) failure phenomena for prog ram and erase operations the device may fail during a program or erase operation. the following possible failure modes should be consid ered when implementing a highly reliable system. failure mode detection and countermeasure sequence block erase failure status read after erase ? block replacement page programming failure status read after program ? block replacement single bit programming failure ?1 to 0? ecc ? ecc: error correction code. 60 bit co rrection per 1kbyte s is necessary. ? block replacement program erase when an error occurs during an erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). note) (a) block address (pa8 to pa18) can only be selected between block 0 and block 2083. (b) wl address in block (pa0 to pa6) can only be selected between wl 0 and wl 85. input of a address other than specified above is invalid. if those unspecified addresses are inputted in progra m or erase operation, the device will output a fail status to respond to status read command. however, it is not permitted to count such a fail status as a bad block information when those unspecified addresses are input. (12) do not turn off the power before write/erase operation is complete. avoid using th e device when the battery is low. power shortage and/or power failure before wr ite/erase operation is complete will cause loss of data and/or damage to data. (13) the all data which are lower/middle/upper data of the wl can be read out only if 3 rd program is completed when an error happens in block a, try to reprogram the data into another block (block b) by loading from an external buffer. then, prevent further system accesses to block a ( by creating a bad block table or by using another appropriate scheme). block a block b error occurs buffer memory free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 65 package dimensions weight: 0.53 g (typ.) free datasheet http:///
toshiba confidential TC58NVG5T2HTA00 2011-03-23c 67 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collect ively ?toshiba?), reserve the right to make changes to the in formation in this document, and related hardware, software an d systems (collectively ?product?) without notice. ? this document and any information herein may not be reproduc ed without prior written permission from toshiba. even with toshiba?s written permission, reproduc tion is permissible only if reproducti on is without alteration/omission. ? though toshiba works continually to improve product's quality a nd reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for prov iding adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situat ions in which a malfunction or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own applications, cu stomers must also refer to and comply with (a) the latest ve rsions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and applicat ion notes for product and the precautions and condi tions set forth in the "toshiba se miconductor reliability handbook" and (b) the instructions for the application with which the product will be us ed with or for. customers are solely responsible for all aspe cts of their own product design or applications , including but not limited to (a) determining the appropriateness of the use of this product in such design or applications; (b) eval uating and determining the applicability of any info rmation contained in this document, or in c harts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operatin g parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications. ? product is intended for use in general el ectronics applications (e.g., computers, personal equipment, office equipment, measur ing equipment, industrial robots and home electroni cs appliances) or for specif ic applications as expre ssly stated in this document . product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality a nd/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or se rious public impact (?unintended use?). unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic s ignaling equipment, equipment used to control combustions or explosions, safety devices, elevat ors and escalators, devices related to el ectric power, and equipment used in finance-related fields. do not use product for unintended use unless specifically permitted in thi s document. ? do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ? the information contained herein is present ed only as guidance for product use. no resp onsibility is assumed by toshiba for an y infringement of patents or any other intellectual property rights of third parties that may result from the use of product. no license to any intellectual property right is granted by this documen t, whether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provid ed in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, co nsequential, special, or incidental damages or loss, including without limitation, loss of profit s, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related so ftware or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manuf acturing of nuclear, chemical , or biological weapons or missi le technology products (mass destruction w eapons). product and related software and technology may be controlled under the japanese foreign exchange and foreign trade law and the u.s. expor t administration regulations. ex port and re-export of product or related software or technology are strictly prohibited exc ept in compliance with all applicable export laws and regulations. ? product is subject to foreign ex change and foreign trade control laws. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pro duct. please use product in compliance with all applicable laws and regula tions that regulate the inclusion or use of controlled subs tances, including without limitation, the eu rohs directive. toshiba a ssumes no liability for damages or losses occurring as a result o f noncompliance with applicable laws and regulations. free datasheet http:///

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